Small Current MOSFET Holding Circuit Fabrication Application

A MOSFET holding circuit which includes resistors R1-R6, electrolytic capacitors C1-C3, capacitor C4, PNP triode VD1, diodes D1-D2, intermediate relay K1, a voltage comparator, a dual time base integrated chip NE556, and a MOSFET Q1, with pin No. 6 of the dual time base integrated chip NE556 serving as a signal input, and one end of resistor R1 being connected at the same time to Pin 6 of the dual-time base integrated chip NE556 is used as the signal input, one end of resistor R1 is connected to pin 14 of the dual-time base integrated chip NE556, one end of resistor R2, one end of resistor R4, the emitter of the PNP transistor VD1, the drain of the MOSFET Q1, and the DC power supply, and the other end of resistor R1 is connected to pin 1 of the dual-time base integrated chip NE556, pin 2 of the dual-time base integrated chip NE556, the positive electrolytic capacitance of capacitor C1, and the intermediate relay. K1 normally closed contact K1-1, the other end of the intermediate relay K1 normally closed contact K1-1, the negative pole of electrolytic capacitor C1 and one end of capacitor C3 are connected to the power supply ground, the other end of capacitor C3 is connected to the pin 3 of the dual time base integrated chip NE556, the pin 4 of the dual time base integrated chip NE556 is connected to the positive pole of electrolytic capacitor C2 and the other end of resistor R2 at the same time, and the negative pole of electrolytic capacitor C2 is connected to the power supply ground, and the negative pole of electrolytic capacitor C2 is connected to the power supply ground. The negative pole of C2 is connected to the power supply ground, the pin 5 of the dual time base integrated chip NE556 is connected to one end of resistor R3, the other end of resistor R3 is connected to the positive phase input of the voltage comparator, the negative phase input of the voltage comparator is connected to the positive pole of the diode D1 and the other end of resistor R4 at the same time, the negative pole of the diode D1 is connected to the power supply ground, and the output of the voltage comparator is connected to the end of resistor R5, the other end of resistor R5 is connected to the PNP triplex. The output of the voltage comparator is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the base of the PNP transistor VD1, the collector of the PNP transistor VD1 is connected to the positive pole of the diode D2, the negative pole of the diode D2 is connected to the end of the resistor R6, the end of the capacitor C4, and the gate of the MOSFET at the same time, the other end of the resistor R6, the other end of the capacitor C4, and the other end of the intermediate relay K1 are all connected to the power supply land and the other end of the intermediate relay K1 is connected to the source of the the source of the MOSFET.

MOSFET retention circuit, when A provides a low trigger signal, at this time the dual time base integrated chip NE556 set, dual time base integrated chip NE556 pin 5 output high level, high level into the positive phase input of the voltage comparator, the negative phase input of the voltage comparator by the resistor R4 and the diode D1 to provide a reference voltage, at this time, the voltage comparator output high level, the high level to make the Triode VD1 conducts, the current flowing from the collector of triode VD1 charges capacitor C4 through diode D2, and at the same time, MOSFET Q1 conducts, at this time, the coil of the intermediate relay K1 is absorbed, and the intermediate relay K1 normally closed contact K 1-1 is disconnected, and after the intermediate relay K1 normally closed contact K 1-1 is disconnected, the DC power supply to the 1 and 2 feet of the dual-time base integrated chip NE556 provides the supply voltage is stored until the voltage on pin 1 and pin 2 of the dual-time base integrated chip NE556 is charged to 2/3 of the supply voltage, the dual-time base integrated chip NE556 is automatically reset, and pin 5 of the dual-time base integrated chip NE556 is automatically restored to a low level, and the subsequent circuits do not work, while at this time, the capacitor C4 is discharged to maintain the MOSFET Q1 conduction until the end of the capacitance C4 discharging and the intermediate relay K1 coil release, intermediate relay K1 normally closed contact K 11 closed, at this time through the closed intermediate relay K1 normally closed contact K 1-1 will be dual time base integrated chip NE556 1 foot and 2 feet of the voltage release off, for the next time to dual time base integrated chip NE556 pin 6 to provide a low trigger signal to make dual time base integrated chip NE556 set to prepare.

The circuit structure of this application is simple and novel, when the dual time base integrated chip NE556 pin 1 and pin 2 charging to 2/3 of the supply voltage, dual time base integrated chip NE556 can be automatically reset, dual time base integrated chip NE556 pin 5 automatically return to a low level, so that the subsequent circuits do not work, so as to automatically stop charging capacitor C4, and after stopping the charging of the capacitor C4 maintained by the MOSFET Q1 conductive, this application can continuously keep MOSFET Q1 conductive for 3 seconds.

It includes resistors R1-R6, electrolytic capacitors C1-C3, capacitor C4, PNP transistor VD1, diodes D1-D2, intermediate relay K1, voltage comparator, dual time base integrated chip NE556 and MOSFET Q1, pin 6 of the dual time base integrated chip NE556 is used as a signal input, and one end of the resistor R1 is connected to pin 14 of the dual time base integrated chip NE556, resistor R2, pin 14 of the dual time base integrated chip NE556 and pin 14 of the dual time base integrated chip NE556, and resistor R2 is connected to pin 14 of the dual time base integrated chip NE556. pin 14 of the dual-time base integrated chip NE556, one end of resistor R2, one end of resistor R4, PNP transistor

What kind of working principle?

When A provides a low trigger signal, then the dual-time base integrated chip NE556 set, dual-time base integrated chip NE556 pin 5 output high level, high level into the positive phase input of the voltage comparator, the negative phase input of the voltage comparator by the resistor R4 and the diode D1 to provide the reference voltage, this time, the voltage comparator output high level, the high level of the transistor VD1 conduction, the current flows from the collector of the transistor VD1 through the diode D2 to the capacitor C4 charging, at this time, the intermediate relay K1 coil suction, the intermediate relay K1 coil suction. The current flowing from the collector of transistor VD1 is charged to capacitor C4 through diode D2, and at the same time, MOSFET Q1 conducts, at this time, the coil of intermediate relay K1 is suctioned, and intermediate relay K1 normally-closed contact K 1-1 is disconnected, and after the intermediate relay K1 normally-closed contact K 1-1 is disconnected, the power supply voltage provided by the DC power source to the 1 and 2 feet of the dual timebase integrated chip NE556 is stored until the When the voltage on pin 1 and pin 2 of the dual-time base integrated chip NE556 is charged to 2/3 of the supply voltage, the dual-time base integrated chip NE556 is automatically reset, and pin 5 of the dual-time base integrated chip NE556 is automatically restored to a low level, and the subsequent circuits do not work, and at this time, the capacitor C4 is discharged to maintain the MOSFET Q1 conduction until the end of the discharge of the capacitor C4, and the coil of intermediate relay K1 is released, and the intermediate relay K1 normally closed contact K 1-1 is disconnected. Relay K1 normally closed contact K 1-1 closed, this time through the closed intermediate relay K1 normally closed contact K 1-1 will be dual-time base integrated chip NE556 1 feet and 2 feet on the voltage release, for the next time to the dual-time base integrated chip NE556 pin 6 to provide a trigger signal to set low, so as to make preparations for the dual-time base integrated chip NE556 set.